ECHO: Extending Coherence for Hardware-Driven Optimizations in Multicore Architectures
In a multicore architecture, the cache coherence protocol is an essential component since its unique but challenging role is to offer a simple and unified view of the memory hierarchy. This project envisions that extending the role of the coherence protocol to simplify other system components will be the key to overcome the performance and energy limitations of current multicores.
Técnicas Innovadoras en Computación Especializada y de Altas Prestaciones (RTI2018-098156-B-C53)
The project will develop new proposals in the research lines traditionally followed by our group (architecture of the processing node and of the associated memory subsystem, system software, applications and services offered by servers). Additionally, it will also deal with lines such as the design of efficient hardware accelerators for inference processes with DNNs and, likewise, it will develop research on system software for servers, in particular we will seek to improve the performance and availability of parallel file systems.
Principal investigators: A. Javier Cuenca, Manuel E. Acacio
Entidad financiadora: Ministerio de Ciencia e Innovación
Fechas: January 2019 to December 2021
Projects with companies
Exploring the implementation space of Arm’s Transactional Memory Extensions (TME) using gem5
Transactional Memory (TM) is as a conceptually simpler programming model that can help boost developer productivity by eliminating the complex task of reasoning about the intricacies of safe fine-grained locking.The objective of this project is to extend the widely used gem5 simulator with TM support in order to evaluate the performance of transactional workloads on the Arm architecture under a range of HTM implementation alternatives.
Principal investigator: J. Rubén Titos-Gil
Researchers: Alberto Ros, Manuel E. Acacio, Ricardo Fernández
Empresa: Huawei Technologies CO., LTD.
Fechas: April 2021 to September 2021Funding: 71.400€ (charitable donation